The present invention relates to a method of reading a flash memory device, and more particularly, to a method of reading a flash memory device for depressing read disturb.
A flash memory device is widely used in diverse electronic applications for non-volatile memory devices. A flash memory device utilizes one transistor cell, and is therefore able to provide high memory density and reliability and low power consumption. A flash memory device is used in portable computers, personal digital assistants (PDAs), digital cameras, mobile phones, etc. Also, program codes, system data such as a basic input/output system (BIOS), and firmware can be programmed into flash memory devices. Among flash memory devices, NAND flash memory devices have high memory density at a relatively low cost, so that the range of its applications is gradually expanding.
As illustrated in FIG. 1, a memory cell of a NAND flash memory device includes a plurality of cell strings. A cell string 100 includes a drain select transistor 110, a plurality of memory cells 131, 132, 133, and 134, and a source select transistor 120, which are all connected in series. A drain of the drain select transistor 110 is connected to a bit line BL, and its source is connected to a drain of the memory cell 131. A gate of the drain select transistor 110 is connected to a drain select line DSL. Gates of the memory cells 131, 132, 133, and 134 are respectively connected to word lines WL1, WL2, WL3, and WL4. A drain of the source select transistors 120 is connected to a source of the memory cell 134, and its drain is connected to a common source line CSL. A gate of the source select transistor 120 is connected to a source select line SSL. The drain select transistor 110 and the source select transistor 120 are conventional MOS transistors, and the memory cells 131, 132, and 133 are floating gate transistors.
The memory cells 131, 132, 133, and 134 have an erased state or a programmed state, respectively, according to their threshold voltages. The memory cells in an erased state have a relatively low threshold voltage, e.g., lower than approximately ground voltage, for example 0 V. On the other hand, the memory cells in a programmed state have a relatively high threshold voltage, e.g., higher than approximately ground voltage, for example 0 V. A read operation that determines which state the memory cell is in applies a read voltage, e.g., approximately ground voltage, for example 0 V, to a word line of the selected memory cell and then determines whether the selected memory cell maintains a turned-on or a turned-off state. That is, if the selected memory cell is turned on, the selected memory cell is in an erased state because its threshold voltage is lower than a read voltage. On the other hand, if the selected memory cell is turned off, the selected memory cell is in a programmed state because its threshold voltage is higher than a read voltage.
Due to the repeated read operations, a read disturb phenomenon may occur. In the read disturb phenomenon, the threshold voltage of an erased memory cell abnormally increases, and this is read as a programmed state instead of an erased state. There are various factors that cause the read disturb phenomenon, and one of them is hot carriers.
Specifically, as illustrated in FIG. 2, while reading a memory cell 132, a read voltage Vread of approximately ground voltage, for example 0 V is applied to a word line WL2 of a selected memory cell, and a pass voltage Vpass of approximately 5 V higher than the read voltage Vread is applied to word lines WL3 and WL4 of the remaining transistors, i.e., the unselected memory cells 133 and 134. Due to the pass voltage Vpass applied to the word line WL3, channel boosting occurs at the unselected memory cell 133 adjacent to the selected memory cell 132. Accordingly, referring to arrows 241 and 242, strong horizontal and vertical electric fields are formed. Due to the horizontal and vertical electric fields, as illustrated in the arrow 243, electrons forming an off-leakage current at the channel of the selected memory cell 132 become hot carriers with high energy and then are injected to a floating gate FG of the unselected memory cell 133 adjacent to the selected memory cell 132. Then, a threshold voltage of the memory cell 133 increases, such that the memory cell 133 abnormally changes from an erased state into a programmed state.
As described above, the read disturb phenomenon due to the hot carriers occurs, because the pass voltage, e.g., of approximately 5 V, is applied to the drain select line DLS of the drain select transistor 110 of FIG. 1, and a pass voltage, e.g., of approximately 5 V, is simultaneously applied to the word line WL3 of the unselected memory cell 133. Since the pass voltage is simultaneously applied to the drain select line DSL of the drain select transistor 110 and the word line WL3 of the memory cell 133, the channel boosting occurs in a channel region of the memory cell 133, and the vertical and horizontal electric fields are formed due to the channel boosting.